FPM DRAM (Fast Page Mode DRAM)

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FPM DRAM (Fast Page Mode Dynamic Random Access Memory) is a dynamic memory with the fast page access which ensures a higher perfomance than the conventional dynamic random access memory (DRAM).[1] The main dfference from the previous generation of memory is the support of abbreviated addresses. If the next requested cell is in the same line as the previous one, its address is uniquely determined by only the column number and the line number is not needed. How is this achieved? When using the normal DRAM the RAS (Remote Access Services) [2] signal is desactivated after reading data to prepare the chip for the next exchange cycle. FPM-DRAM controller keeps RAS in the low state to get rid of the retransmission of the row number.

SIMM Sockets with RAM.jpg

History

FPAM memory appeared in 1990. It used a 64-bit bus width, a voltage of 5 volts and had a capacity of up to 200 Mbit per second at a frequency of 25 MHz. In 1995 EDO DRAM (Extended Data Out DRAM) (40 MHz) replaced FPAM and was replaced later in 1996 by SDRAM (up to 133 MHz). There are quite a few different dynamic memory options, slightly different from each other in the principles of data access. The conventional DRAM dynamic memory has been out of use for a long time now. In the mid-90’s it was replaced by a modification of the PM DRAM dynamic memory (Page Mode DRAM) - FPM DRAM memory. The basic difference from FP DRAM memory was in the support of the stored addresses. That is, if the new word, which is read from memory, is in the same line as the previous one, then the address to the memory array is not required, and the data selection is being carried out from the “data buffer” by the column number. In the case of reading data from memory arrays, this helped to significantly reduce the reading time. However, writing data was implemented in the same way as in the PM DRAM memory. Also, not always the data reads were located in the same line. As a result, the performance gain was strongly dependent on the type of software working on computers. The gain could be significant or the work could slow down, due to the additional expenses on the line number analysis of the previous reading operation.

Principle of operation

The operating principle of FPM-memory is based on the assumption of a sequential data access: it is assumed that the data to be accessed is arranged in series within the same row of the memory array. The page in this case is the matrix row. The meaning of a page access mode is that after selection of the row and retention of RAS, there may be a multiple installation of the column address, gated by CAS. This approach allows the selection of the serial data within one line without changing its address, that is, with one and the same RAS signal. This speeds up the block transfer, but only in the case when the entire block of data or a portion thereof is within a single row of the matrix. Bits are stored in the memory cells arranged as a matrix consisting of rows and columns. Like all the other types of DRAM, in IC memory of this type there’s only half of all the outputs necessary to indicate read or write data addresses. The memory cycle begins with the location of the first line, which requires half of the address bits, and then a column address of the data, which is the other half of the address. Then, there’s the reading or writing of data. The fast page exchange mode allows addressing the next column, which corresponds to the following in order of memory address, without re-specifying row. This makes it possible to reduce the access time in order to read the next several memory cells, provided that this has not yet reached the end of the line, thereby increasing the productivity. FPM DRAM memory cycle time is 50 ns, which allows you to maintain access to the memory with a frequency of 30 million times per second, or 30 MHz. This is sufficient for the memory bus clocked at 60 or 66 MHz, typical for the Pentium processor. So, for the memory access it requires more than one cycle, and this is done in batch mode, therefore, the memory address is not needed to be indicated with each access. This is possible because memory access is usually carried out in reference to the ordered memory cells, and if it is not, then the additional memory access data is not used or ignored. Access to memory in batch mode is usually indicated by the formula 6-3-3-3, which means that the first memory access requires 6 clock cycles, because it is necessary to completely specify the address, and for each of the three subsequent applications only 3 clock cycles are required. Typically, the clock cycles are executed with a memory bus speed of the processor. Often, this corresponds to a clock frequency of 60 or 66 MHz, with the internal clock speed of the processor, respectively, 120 or 133 MHz.

FPM DRAM System:

FPM DRAM System

Application

The dynamic memory with the fast page access is actively used by 80386 and 80486 chips. [3]

Special features

The main difference from the previous generation of memory is the support of abbreviated addresses. If the next requested cell is in the same line as the previous one, its address is uniquely determined by only the column number and the line number is not needed. How is this achieved? When using the normal DRAM the RAS (Remote Access Services) signal is desactivated after reading data to prepare the chip for the next exchange cycle. FPM-DRAM controller keeps RAS in the low state to get rid of the retransmission of the row number. When using the sequential reading of memory cells (as well as the processing of compact one- or two-kilobyte data structures), access time is reduced by 40%, and even more, because the processed line is in an internal buffer chip, and there is no need to access the matrix memory! [4]!

Note

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  1. FPM (Fast Page Mode) DRAM [Electronic resource] : Material from http://www.aten.ru/: — Access mode: http://www.aten.ru/articles/artview.php?idx=23
  2. Remote Access Services [Electronic resource] : Material from http://rsdn.ru/: — Access mode: http://rsdn.ru/article/net/rasstat.xml
  3. Static and dynamic RAM [Electronic resource] : Material from http://pandia.ru/: — Access mode: http://pandia.ru/text/78/135/91022.php
  4. Memory - from the depths of time to our days : Material from http://citforum.ru/: — Access mode: http://citforum.ru/book/optimize/ram.shtml