BEDO DRAM (Burst Extended Data Output DRAM)
This page was last modified on 15 December 2016, at 21:06.
BEDO DRAM (Burst Extended Data Out Random Access Memory) - a faster type of EDO, memory with an improved outcome. BEDO RAM gained its speed by using an address counter for next addresses and a pipeline stage that overlapped operations.
BEDO RAM reads data from a package, which means that after receiving addresses each of these three pieces of information is read for one cycle of the timer, and the CPU reads the data packet in a 5-1-1-1. This RAM model is currently supported only on VIA chipsets 580VP type, 590VP, 680VP.
By adding a chip generator column number, the designers eliminated the delay CAS Delay, reducing cycle time of 15 ns, thus providing a two-fold increase in productivity. After the conversion to an arbitrary cell chip BEDO automatically, without instructions from the controller increases the number of columns per unit, without requiring its explicit transmission. Because of the limited bit address counter (designers allocate to it just two bits), the maximum packet length can not exceed four cells.
Additional registers package provides a quick output a string of serial addresses. Looking ahead, we note that the Intel 80486 and Pentium processors due to batch exchange mode, the memory never treated with at least four adjacent cells at a time. Therefore, regardless of the order data access BEDO always work at the highest possible speed and the frequency of 66 MHz of its formula is as follows: 5-1-1-1, which is ~ 40% faster than EDO-DRAM.
Despite its high-speed performance, BEDO was not competitive and did not receive any spread. Miscalculation was that EDO like all its predecessors, remained asynchronous memory. This situation imposes severe limitations on the maximum achievable clock speed, limited to 60 - 66 (75) MHz.
Since the "clock" of the memory controller and the most memory chips are not synchronized, there is no guarantee that the beginning of the memory chip cycle coincides with the beginning of the pulse controller itself, so the minimum waiting time is two cycles. Rather cycle working memory chips never coincides with the beginning of the clock pulse. Or rather, cycle working memory chips never coincides with the beginning of the clock pulse.
It takes a few nanoseconds to form the controller of the control signal RAS or CAS, therefore it doesn't coincide with the start timing pulse. Just a few nanoseconds is required to stabilize the signal and its processing by chip. We can not determine the necessary time, because temperature, length of the conductors, noise on the line and another set of factors affects the result.This type of memory supports only one set of Intel 440FX Nato ma system logic. Currently BEDO replaced by a new type of SDRAM memory. The main disadvantage BEDO RAM is also inability to work on the bus speed in excess of 66 MHz.
Plus, there was a special need for a controller BEDO, no one wanted to change a motherboard. Although BEDO RAM was used in the Pentium Pro-based systems.
Except for support of fast bus speeds, BEDO would probably have been a much faster and more stable memory than SDRAM. Essentially, BEDO lost support as much for political and economic reasons as for technical ones, it seems.
Difference between BEDO and EDO
Accessing VEDO for reading has two differences from access to EDO:
- The first of these is that the data do not get to the outputs by replacing the latch register in the first CAS cycle. The advantage of such an internal conveyor unit: in the second cycle time of occurrence of the data after issuing the leading edge CAS becomes smaller.
- BEDO systems contain internal address counter, they receive only the one of four consecutive addresses from the outside. Simplified scheme of BEDO and the sequence of events shown in the figure. These three figures illustrate tPC gradual reduction as we move from FPM to EDO and further to BEDO, and also show that by using BEDO DRAM tCAC decreases and tCPA reduces to zero. The figure also shows that the BEDO first CAS cycle loading internal conveyor unit does not lead to delay in receipt of the first data element, because of the access time to the first data element is determined tRAC (access time for RAS), which overlaps the first CAS cycle.
BEDO RAM support
BEDO RAM was supported by the following chipsets:
- VIA Apollo VP
- OPTi ViperMax
- PCChips VXPro
- PCChips VXPro+
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- Файловый архив студентов [electronic resource]: Организация оперативной памяти / treatment date: 30.11.2016. - Access:http://www.studfiles.ru/preview/3860012/page:14/
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