VHDL (VHSIC Hardware Description Language)

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This page was last modified on 1 June 2016, at 16:44.
VHSIC Hardware Description Language
Paradigm Hardware description language
Designed by The US Department of Defense
First appeared 1983
Typing discipline strict
OS Windows, OS X, Linux
Filename extensions .vhd
Website http://accellera.org/
Influenced by
Ada, Pascal

VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. It was developed in 1983 for the Ministry of Defense for the purpose of the formal description logic for all stages of the development of electronic systems, from chips and modules to large computer systems. VHDL can be used as a general purpose parallel programming language.


The original language designed for modeling, but later it was allocated from the synthesized subset. Writing model synthesized subset allows automatic synthesis scheme is functionally equivalent to the original model. By means of VHDL design possible at various levels of abstraction (or algorithmic behavioral, register transfer, structural), in accordance with technical requirements and preferences of the developer. Is the possibility of a hierarchical design, as much as possible to realize their extremely large projects involving a large group of developers. It is possible to distinguish the following three components of language: the algorithmic - based languages, Ada, and Pascal, and conferring properties of VHDL programming languages; problem-oriented - in the spirit and draws in the VHDL hardware description language; and object-oriented, vigorously developing in recent years.

Standards 1987, 1991, 1993, 1996, 1997, 1999, 2000, 2002 and 2008. fixed many of its improvements, such as starting with the standard VHDL-2000 language acquires the basics of object-oriented paradigm. Standard VHDL-93 is the latest, fully supported by means of CAD standard [citation 2040 days].

VHDL created as a means of describing digital systems, but there is a subset of the language - VHDL AMS (Analog Mixed Signal), which allows to describe as a purely analog and mixed, digital-to-analog circuitry.

Primary abstraction of VHDL

VHDL is a formal record for describing the digital system. The function of the system is defined as the transformation of the values at the inputs to the output value. Organization of the system is given a list of related components.

Object of the project

The object of the project entity is a description of the components of the project, which has clearly defined inputs and outputs, and performing a clearly defined function. The object of the project can provide all the projected system, a subsystem, a device node, rack, card, crystal, macrocell, gate, etc.

Project hierarchy

In the description of the design entity can use components which, in turn, may be described as independent objects project lower level. The combination of these connected objects project called "hierarchy of the project" design_hierarchy .

Types descriptions

Each design entity consists of at least two different types DESCRIPTION: interface and one or more architectural bodies.

In the description of digital systems in the language VHDL, the user can use five different types of descriptions:

  • The interface is described in the declaring the object of the project entity_declaration defines only the inputs and outputs of the project object.
  • To describe the behavior of an object or its structure is architectural body architecture_body .
  • To specify which objects project used to create a complete project using ad configuration configuration_declaration .
  • In a VHDL package provides a mechanism for commonly used definitions, constants, types of signals. These descriptions are placed in the ad package package_declaration .
  • If the user uses a non-standard operations, or functions, their interfaces are described in the package declaration and body are in the package body package_body .

Project module

Each description is an independent design language VHDL, can be independently analyzed by the analyzer and therefore has been called module of the project design_unit . The modules of the project, in turn, can be divided into two categories:

  • primary (various types of ads)
  • secondary (separately analyzed the body of primary modules)

One or more modules of the project can be put into one file called project file design_file .

Each module analyzed the project is placed in the Library Project design_library and becomes library unit library_unit . This implementation allows you to create any number of project libraries. Each library project in VHDL language has a logical name (ID). The actual name of the file containing the library may or may not coincide with the logical name of the library project. To associate the logical name of the library with the appropriate real name she has a special mechanism for setting of external links.

In relation to the work of the session, there are two classes of VHDL design libraries: library workers and library resources. Working Library - a library, which in this session and the user is working in a library module which is placed, resulting from the analysis module project.

Resource Library - a library containing library modules, the reference to which there is in the test module of the project.

At any given moment you are working with a working library, and an arbitrary number of library resources.

Ability to create and use many libraries allow the user to classify the resource library modules on various grounds. For example, one library contains descriptions of a series of chips in the other - describe another series of chips, etc. Or in a single library to store descriptions of chips with one type of delay, the other - to describe another type of chip delays, etc.

Lexical elements

Any computer language is characterized by a certain set of allowed lexical elements. Text descriptions in VHDL language is composed of one or more project files. The project file is a sequence of lexical elements, each of which is composed of the characters well-defined set of characters. The text of each module of the project is a sequence of individual lexical items.


Limiter can be one of the following characters (included in basic set): '() * + -. /: <=> |

Limiter can also be one of the constituent constraints, made up of special characters standing nearby:

lim. name
=> arrow
** double star, exponentiation
:= variable assignment
/ = not equal
> = more or equal
<= less than or equal, and signal assignment
<> block


Identifiers are used as the name, and as reserved words. Identifiers may contain letters in upper and lower case, numbers, and the underscore character. Uppercase and lowercase letters are considered equivalent identifiers. Since the gap is the delimiter, then it is unacceptable to use in the ID.



Comments begin with two adjacent characters hyphen and limited end of the line. A comment It can appear in any line of VHDL-description. The presence or absence of comments has no effect the correctness of description. Moreover, the comments do not affect the performance of the module modeling; the sole purpose of comments is to improve the readability of the description. Horizontal tab can be used in a comment after the double hyphen character and it equivalent to one or more spaces.


Decimal abstract literal Abstract literal expressed in the decimal system. The underscore is standing between two adjacent numbers, it does not affect the value of the literal. The letter E in terms of exhibitors (if used) can be written in any case. Expression of exhibitors generally literal must not contain a minus sign. The abstract literals allowed zeros. Since the gap is a delimiter, it is not permitted in abstract literals, even between components of the exhibitors. A value of 0 exhibitors is allowed only in integer literals. 11, 1E6, 0, 123_456, 3.141_592, 11.0, 0.331, 6.023E + 24 2.64E-12, 1.0E + 6
Based abstract literal Abstract literal expressed in a form that explicitly includes base notation (2 to 16). The underscore is standing between two adjacent numbers, it does not affect the value of the literal. Base radix (base) and the exhibitor shall be expressed as a decimal number. The letter was based in the literal (whether in the exponent letter E or extended digit) can be written in any case. Exhibitor database indicates the degree to which the value is multiplied based literal taken without expression exhibitors to get the value of this literal with exponent. Expression of exhibitors generally literal must not contain a minus sign. 2 # 1111_1111 # 16 # FF # 016 # 0FF #, 16 # F.FF # E + 2, 2 # 1.1111_1111_111 # E11
Character literal Formed by including one of the 95 graphic characters (including the space character) between two characters apostrophe. A character literal contains a value of type character. 'A', '*', ,
A string literal Formed from a sequence of graphic symbols (possibly empty) enclosed between two quotation mark used as string brackets. A string literal is a value that represents a sequence of character values ​​corresponding to the graphic symbols of the string literal except themselves quotes. If you want to include a quote character in the string literal, then this symbol must be repeated two consecutive times at the appropriate place. The length of a string literal is the number of character values ​​in the sequence shown. (Each double quote character is read as a single character). A string literal must be written on one line, because it is a lexical item. "Setup time is too short", "", "", "A", "" ""
Bits-string literal Bits-string literals bit-string literal are formed of a series of extended figures, concluded between the two quote character used as a bit string braces and preceded by a qualifier base base specifier . Specifier base can be set to B, G, and H. If the specifier is a numeral in the base, in an extended numbers can serve only the digits 0 and 1; If O, the digits from 0 to 7; and if X, then the numbers 0 through 9 and A through F. The underscore is standing between two adjacent numbers in the bit-string literal does not affect the value of this literal. The letters used as the expanded figures are letters from A to F, representing, respectively, the numbers from 10 to 15. The letter in the bit-string literal (extended figure or specifier base) can be written in uppercase or lowercase in the form - literal value does not change.

Bits-string literal is a value that represents a sequence of values ​​of predefined type BIT (ie a sequence of '0' and '1'). If the base pointer notation yes, then value of the bit-string literal is the very literal. If the index base is O (or X), the literal meaning is the sequence obtained by substituting each extended sequence numbers of the three (or four, respectively) values ​​of predefined type BIT. Bit length-string literal is the number of values ​​provided in the BIT type sequence.

X "FFF", 0, "777", X "777"


Between any two adjacent lexical elements are allowed to put one or more separators, as well as before the first lexical element or after the last lexical item in each module of the project. At least one delimiter is required between the identifier or literal and abstract neighboring identifier, a literal or abstract.

A separator can be a space character or a control character format, or end of the line. The space character is not a separator within a comment, a string literal or character literal, including the symbol.

Reserved words

The identifiers listed below are called reserved words are reserved in language for special purposes.

Reserved words








The keyword should not be used as an identifier declared. Reserved words that differ only in the use of appropriate uppercase and lowercase letters are considered as identical. 1.2.7. Possible replacement characters For basic symbol "vertical bar", "sharp", "quote" allowed the following substitutions: 1) The vertical bar (|) may be replaced by an exclamation mark (!) When used as a stop; 2) Sharp (#) based in the literal can be replaced with a colon (:), and the need to replace both signs in This literal; 3) quotation marks (") used to delimit a string literal, both sides may be replaced on the percent (%). Thus it is necessary to replace the two brackets string and characters of the sequence eliminate all the characters quotes. Each symbol percent within the sequence of characters should be doubled. Double the percent symbol is interpreted in this case as a single character. Such substitutions do not change the meaning of the description. Terms of Use literal and abstract identifiers such that uppercase and lowercase letters It can be used without distinction. These lexical elements can thus be written using only the basic character set.

Data models in VHDL

Data models allow you to create different types of objects based data base predefined types. Any data object is characterized by a certain class and type. Data objects (data_object) are repositories of values for a particular type. All types in VHDL constructed from elements representing scalar types.

Scalar types

The scalar (scalar) types - the elements of which are constructed in all types of VHDL. The base set scalar types is predefined. As necessary, the developer may create additional scalar types. In VHDL, there are four types of scalar types: a type, floating point enumerated type (enumeration) and physical type. The developer has the opportunity to ask subtypes scalar types.


The objects of a type used to represent an abstract numerical values. The type integer is predetermined. It covers all the integers, limited bit word computer.

Plus the whole types can be declared explicitly by specifying a range of values ​​allowed for objects of this type. Here are some examples of ads integer types.

type Apples is range 0 to 75;
type Oranges is range 0 to 75;
type Word_index is range 31 downto 0;

Consider how to declare objects that use these types.

variable Macintosh: Apples;
variable Seville, Valencia, av_oranges: Oranges: = 10;
signal control_selector: Word_Index;

Constants must be set at the time of the announcement. Similarly, the initial value may be It is assigned to the variable.

All the usual arithmetic and relational operators are predefined for a type. However, both parameters of the operator must be the same type.

You can not compare objects of different types.

However, all integer types and floating-point types are closely related types of closely related types and VHDL provides for these types of transformation conversion between any pair. The value expression of the same type is converted to the value of closely related to the type of indication expression enclosed in parentheses, the name of the type to which the expression is converted. When converting between the type of floating-point and integer type will be carried out rounding to the nearest integer.


Objects floating-point type used to represent an abstract numerical values. A type real is predetermined. It includes real numbers. Additional floating-point types can be declared explicitly by specifying a range of values, valid for objects of this type. Consider the example of ads floating-point type.

 type Probability is range 0.0 to 1.0;

Ranges are given by either decreasing or increasing values ​​sequence. Boundaries range may be arbitrary expressions. Consider how to declare objects that use these types.

constant alpha_level: Probability: = 0.75;
variable beta_level: Probability;

Constants must be set at the time of the announcement. Similarly, the initial value may be It is assigned to the variable. Floating-point literals represent values ​​of any type of floating-point and always contain a decimal point or negative exponent: for example, 3.14159, -23.0, 1E-2. Recording with the exponential can be used for any kind of numeric literals: 9E - whole, and 0.324E-3 - float. For the formation of expression may be used a combination of object names and literals operators. All the usual arithmetic and relational operators are predefined for the type float. However, both parameters of the operator must be the same type. Predefined operator ">" does not work with operands of different types, even if they have the same range. All integer types and floating-point types are closely related types of closely related types and VHDL provides for these types of transformation conversion between any pair.

Enumeration types

Type consists of a plurality of possible values ​​that can take the objects of this type, together with a plurality of operations on the type. The ad explicitly enumerated type identifiers are listed and graphics that mean values ​​of the type. Identifiers and symbols are literals type in the same way as the 3 and 245 are integer literals. Values ​​and attitudes are ordered ordering determined by the sequence of their appearance in the list. Consider a few examples:

type severity is (OKAY, NOTE, WARNING, ERROR, FAILURE);
type color is (red, orange, yellow, green, blue, indigo, violet);
type bit6 is ('U', '0', '1', 'F', 'R', 'X');
type fuzzy_logic is ('0', may be, '1');

No need to write ads for the following enumeration types, because they are predefined:

type character is (NUL, ..., 'A', 'B', 'C', ... DEL);
type boolean is (False, True);
type bit is ('0', '1');

Type character symbols to include all printable and non-printable elements of code ASCII, as well as their graphic representations. The logical operators and, or, nand, nor and xor defined for operands of type bit or boolean type and give the result of the same type as the operands (but you can not specify one operand of type boolean, and the other type of bit). Relational Operators "=", ">", "> =" and others give a boolean result no matter what types of operands.

Do not confuse the two values ​​of the symbol "<=". This symbol is used as a signal in the appointment value of an expression, and represents the ratio of "less than or equal to".

Subtypes are scalar types

If it is desired that the scalar value of a received object type from a limited range, this may be reflected in the draft text using the ad subtype and use. Assume For example, the developer wants to create a signal A-type and severity that A can only take values OKAY, NOTE and WARNING.

type severity is (OKAY, NOTE, WARNING, ERROR, FAILURE);
subtype go_status is severity range OKAY to WARNING;
signal A: go_status;

Ad subtype determines the basic type base type and limiting the range of range constraint . Any the value assigned to A, must be of severity, which is the base type for Program A. simulation will check whether it falls in the value range OKAY to WARNING, at the time execution destination. If this is not performed, the simulation will be stopped and will be granted a message describing this violation. Basic type and range restriction can be incorporated directly into the classified object, if available bit objects which must be declared with a certain subtype. Consider ad is equivalent to declaring a subtype and a signal above:

signal A: severity range OKAY to WARNING;

The choice of two methods for determining the subtype depends on the convenience. Since the operators are determined for types, not subtypes, the objects of a common base type can freely used in the same expression.

type Counter is range 0 to 100;
subtype low_range is Counter range 0 to 50;
subtype mid_range is Counter range 25 to 75;
subtype hi_range is Counter range 50 to 100;
variable low_count: low_range;
variable mid_count: mid_range;
variable hi_count: hi_range;
mid_count: = (hi_count + low_count) / 2;

Values ​​hi_count low_count and both have type Counter. First, we calculate the value of expression. Then to execution destination, this value is tested using a range of restrictions for mid_count.

Physical types

Physical types allow the developer to directly express the value in physical units measurement. In VHDL, use the same physical type - predefined physical type TIME (time). Ad physical type defines the set of units, defined in terms of a basic unit. In the case of a TIME base unit is fs (femtosecond) and derived units are ps, ns, us and so on. Consider the definition of the type TIME.

type TIME is range - (2 ** 31-1) to 2 ** 31-1
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us;
s = 1000 ms;
min = 60 s;
hr = 60 min;
end units;

A TIME range determines the range of the base units that can be accurately represented object type. Physical literals, using any of the defined names to the physical units will be automatically converted to femtoseconds.

Arrays and records

VHDL provides two kinds of the constituent types that support binding include arrays and records.


'Solid' 'represented by a set of one or more identical elements, considered as a one-dimensional vector, two-dimensional matrix or arbitrary rectangular structure of higher dimension.

Ads arrays

The type declaration for an unlimited array unconstrained is given by the number of indexes, type (index!) And position each index, and the type of array elements. It is not determined by the number of elements in each dimension array. Unlimited massive types in the following list are predefined:

type bit_vector is array (natural range <>) of bit;
type string is array (positive range <>) of character;

Each of these has a single dimension. Type bit_vector indexed predefined values such as natural and has elements of type bit. The string type is indexed predefined type and has a positive elements like character. Recording range <> (pronounced "box range" - range box) means that delimitation of the index has been postponed. Boundaries are substituted when the object is created type.

Comment. As can be seen, in contrast to most programming languages ​​(C, Pascal, Fortran, etc.)., In VHDL, you can specify the type of array indices. The indices of the array may be an integer or enumerated type. The elements may be of any type. For example:

type matrix is ​​array (integer range <>, integer range <>) of real;
type color_accumulator is array (color range <>) of natural;
type color_match is array (natural range <>) of color;
type bit6_data is array (positive range <>) of bit6;
type bit6_address is array (positive range <>) of bit6;
type transition_delay is array (bit6 range <>, bit6 range <>) of time;
type conversion_vector is array (bit6 range <>) of bit;

Announcement of object array type specifies the name and type of restriction on the index (index constraint):

variable square: matrix (1 to 10,1 to 10);
signal A_register, B_register: bit6_data (63 downto 0);
signal parts_per_color: color_accumulator (green to indigo);
constrant part_id: string: = "M00368";
variable bit_equivalence: conversion_vector (bit6);

Each index position in the declaration of an object of type array, which uses a type of unlimited, It must be limited. The range may be limited to:

  1. Using to or downto (first three examples);
  2. It can also be replaced by a range of initial value (in part_id);
  3. Range can be named after the index of the corresponding enumerated type (in bit_equivalence).

The latter range is the full range of enumerated type.

In the case where a greater number of objects of a certain type with the same restrictions on the codes, can be convenient for this purpose to declare subtype. Name subtype can be used in as an abbreviation for a full subtype designations:

subtype data_store is bit6_data (63 downto 0);
signal A_reg, B_reg: data_store;
subtype transform is matrix (of 1 to 4, 1 to 4);
variable X, Y: transform;
signal unit: transform;

There is also another shorthand that is often useful in creating arrays. Consider the next couple of announcements:

type transition_delay is array (bit6 range <>, bit6 range <>) of time;
subtype cmos_transition is transition_delay (bit6, bit6);

These ads can be written as follows:

type cmos_transition is array (bit6, bit6) of time;

The difference is that the type of unrestricted massive transition_delay never explicitly determined. This declaration creates an anonymous type (anonymous type) ad that looks like Ads for transition_delay, immediately followed by an ad for a subtype cmos_transition c According to the restriction on the index.

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