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PC3-10600 DDR3 SO-DIMM (204 pins)
|Type||Synchronous dynamic random-access memory (SDRAM)|
|Release date||26 Jun 2007|
DDR3 SDRAM (Double-Data-Rate Three Synchronous Dynamic Random Access Memory) — the type of RAM, which is an evolution of the previous generation DDR2 SDRAM, which uses a technology called "frequency doubling".
The effective frequency of the DDR3 memory is 1066 to 1600 MHz (also available and more high-speed modules for enthusiasts, operating at a frequency of 1800 MHz and above). Besides the enhanced bandwidth, DDR3 also characterized by low power consumption (save up to 40%) compared with DDR2, due to low (1.5 V compared to 1.8 V for DDR2 and 2.5 V for DDR) of the voltage of the memory cells. This can improve energy efficiency and reduce heat generation. The decrease in voltage is achieved through the use of more thin technical process (in the beginning of 90-nm and later 65, 50, 40 nm) in the manufacture of memory chips and application of transistors with dual-gate Dual-gate (thereby reducing leakage currents).
Other innovations implemented in DDR3, are the dynamic termination signals (dynamic On-Die Termination, ODT) and a new technology of calibration signals. ODT technology allows the flexibility to optimize the value of terminal impedance depending on the load conditions of memory
Thus the main advantages compared to DDR2 is:
- higher bandwidth (up to 2400 MHz)
- increased efficiency with low power consumption
- improved design, conducive to cooling
In Fig.1 shows a micrograph of the chip of DDR3 memory, which is 78 nm at the plant, Micron, and Fig.2 is its block diagram.
In table 1 shows the characteristics of the memory chips of three generations of DDR SDRAM.
|Feature||DDR SDRAM||DDR2 SDRAM||DDR3 SDRAM|
|Voltage, V||2,5+- 0,2||1,8+-0,1||1,5+-0,075|
|Data synchronization||Single ended||Single ended/ Differential||Differential Default|
|Pulse width, clock cycles FSB||2, 4, 8||4, 8||4 (Burst Shop), 8 cell|
|The preliminary portion choice at||2||4||8|
|The number of banks||4||4/8||8|
|The load on the crystal||No||Yes||Yes|
|Calibration||-||Off-Chip Driver Calibration||Self Calibration with ZQ Pin|
- 1 The story of the emergence of DDR3 RAM on the market
- 2 The main differences from DDR2 SDRAM to DDR3 SDRAM
- 3 Manufacturers of chips and memory modules
- 4 References
- 5 See also
The story of the emergence of DDR3 RAM on the market
DDR3 SDRAM appeared on the market early in the third quarter of 2007 simultaneously with the serial Board on the NMS Intel P35 Express, the first sets of system logic-compatible memory modules the new generation. The bandwidth of your system memory for the most common at the time of the RAM modules that meet the specifications PC2-6400, was 6.4 GB/s For DDR3 memory PC3-8500 this feature was slightly higher, 8.5 GB/s. With regard to dual-channel operation mode the theoretical peak performance increased from 12.8 to 17.1 GB/s for DDR2 and DDR3 RAM respectively.
The latency of the first DDR3 modules are not allowed to provide the advantage of higher speed RAM over dominant in the market with DDR2 memory, mass production of which more than covered all the queries of the industry. The situation was exacerbated by the fact that the prices of a new type of memory, as so often happens with new products that were not affordable to ordinary users. Not too big advantage, which showed a PC with DDR3-1066 SDRAM has forced the major suppliers of computer equipment to be limited to small quantities of DDR3 systems. In other words, at first the market met the DDR3 memory is pretty cool.
The situation remained exactly as long as was announced (and then available for order) DDR3-modules are stably operating at a frequency of 1333 MHz and 1666 MHz. In the fall of 2007 appeared first on NMS motherboard Intel X38 Express. The new memory controller (in terms of the Intel hub Memory Controller Hub, the chipset Intel 82X38) provide the interaction platform with modules of RAM DDR2 and DDR3 SDRAM, equipped with the parity function, ensuring peak throughput in dual channel mode to 21.2 GB/s. Gradually decreased to acceptable values of latency, however, the price of 1 MB of memory still remained quite high.
The turning point came in the spring of 2008, when the exhibition CeBIT’2008 was officially announced the chipset Intel X48 Express. Among its features was proprietary technology Intel Fast Memory Access and Intel Flex Memory. The first increased the system performance by increasing bandwidth and reducing time delays on the basic operations of the memory access due to the improved architecture of the bus lines of the Intel 82X48 MCH. The second simplified the upgrade of the memory subsystem, allowing the installation of the system DRAM modules of different size. Of course, the set has provided the possibility of organizing a dual-channel memory mode (peak bandwidth of 25.6 Gbytes/c to DDR3-1600 SDRAM), and filling of up to 8 GB of RAM address space that causes a quick response so necessary for 64-bit computing.
The main differences from DDR2 SDRAM to DDR3 SDRAM
The fundamental difference and the main advantage of DDR3 memory from DDR2 is in its higher frequency operation, which is achieved with the arrangement 8n-Prefetch (8-bit prefetch) vs 4n-Prefetch in DDR2. For the organization of the memory required to buffer I / o (multiplexer) worked at a frequency eight times greater compared to the frequency of core memory. This is achieved as follows: the kernel memory, as before, are synchronized by positive edge of a clock pulse and with the arrival of each positive front on eight independent lines in the input buffer-output (multiplexer) 8P transmitted bit of information (sample size 8P bits per clock). The input buffer output is clocked at quadruple the frequency of core memory and synchronized as the positive and the negative edge of this frequency. This allows for each cycle of operation of the memory core to transfer eight words on the data bus, that is, in eight-fold increase in memory bandwidth.
In Fig.3 shows the frequency response principles of operation of the SDRAM chips of different generations.
Also note that the number of logical banks in DDR3 chips doubled compared to the typical value for DDR2 (4 banks) and is 8 banks that allows you to increase the "parallelism" when referring to the scheme of alternation of logical banks and to hide the latency associated with using one and the same row of memory (tRP).
Fly-by architecture and level control read/write
A distinctive feature of circuit design, DDR3 memory modules is the use of "through" or "span" (fly-by) architecture transmission of addresses and commands, and control signals and clock frequency of individual chips of a memory module by using an external termination signal (resistor located on the memory module). This means that the signals are all chips of the module simultaneously, and consistently. Schematically this architecture is shown in Fig. 5. It allows to increase the quality of signal transmission, which is necessary for the functioning of the components at high frequencies, typical of DDR3 memory and is not required for components of memory of standard DDR2.
The difference between the method of delivery of addresses and commands, control signals and clock to memory modules DDR2 and DDR3 (for example modules, a Bank which is composed of 8 chips bit x8) is shown in Fig. 6. In the DDR2 memory modules supply addresses and commands are carried out in parallel on all the chips of the module, in this connection, for example, when reading data, all eight 8-bit data elements will be available in the same time (after the filing of the respective teams and the expiration of the respective delay) and memory controller will be able to read all 64 bits of data. At the same time, the DDR3 memory modules due to the use of "span" delivery architecture addresses and commands each of the ICS module receives the commands and addresses with a certain lag relative to previous chips, therefore, the data elements corresponding to that particular chip will also be available with some lag relative to the data elements corresponding to the previous chip in the row, constituting a physical Bank of the memory module. In this connection, to minimize delay, the DDR3 compared to the DDR2 modules, implemented a slightly different approach to the interaction of the memory controller with the data bus of the memory module. It's called "level control read/write" (read/write leveling) and allows the memory controller to use a certain shift in time when data transfer corresponding to the "delay" receipt of addresses and commands (and hence data) to a particular chip module. This ensures the simultaneity of the reading (recording) data from the chips (IC chips) memory module.
Incompatibility between modules
DDR3 memory comes in DIMMs (for large computers) or SO-DIMM (for notebooks). As DDR2 memory modules, DDR3 memory is available in a 240-pin printed circuit Board (120 contact with each side of the module) but are not electrically compatible with the latest (taking into account the different supply voltage and different protocols DDR2 and DDR3 SDRAM), and for this reason have a different location of the "key" (see Fig.7). Therefore, to install DDR3 in DDR2 SDRAM DIMM and Vice versa will fail. High quality modules from reputable manufacturers (e.g. Kingston) are only supplied in pairs or sets of three (triple channel), with each module covered with a protective cover or heat sink. Capacity DDR3 memory modules is from 1 to 8 GB.
CompuServe chipset DDR3
IC DDR3 corpusers in FBGA-package with several improvements over DDR2, namely (Fig. 9):
- A large number of power contacts and "ground";
- Improved distribution of power supply and signal contacts, allowing you to achieve the best quality of an electrical signal (necessary for more stable operation at high frequencies);
- Complete the "check-in" arrays, which increases the mechanical strength of the component.
Disadvantages compared to DDR2
Due to the increase in Prefetch, DDR3 has a higher latency or read latency( CAS Latency - the minimum time between the command to the read (CAS) and the start of data transmission) than DDR2 (it is along with high prices for a long time forced the industry to relate to the new standard with caution). For example, if the DDR1 works with latency 2, 2.5 or 3 CAS pulse, DDR3 requires a minimum of 5 clock pulses for the same procedure. However, the increase in clock frequency allows to partly compensate for high latency.
Manufacturers of chips and memory modules
The global sales of DRAM chips manufacturers are located roughly in this order: Samsung, Hynix, Elpida, Micron, Qimonda. In Russia in addition to these firms are often sold memory companies, Kingston, Transcend, Corsair, Patriot, A-Data and OCZ.
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- JEDEC [Internet] : JEDEC Announces Publication of DDR3 Standard / last visited Oct. 26, 2016 - Available from: http://www.jedec.org/news/pressreleases/publication-jedec-ddr3-sdram-standard
- Bytemag [Internet] : Момент истины / last visited Oct. 26, 2016 - Available from: http://www.bytemag.ru/articles/detail.php?ID=12477
- Fcenter [Internet] : DDR3 SDRAM: революция или эволюция? / last visited Oct. 26, 2016 - Available from: http://fcenter.ru/online/hardarticles/motherboards/21754
- Рудометов Евгений. Современное железо. Настольные, мобильные и встраиваемые компьютеры.— СПб.: БХВ-Петербург, 2010. — С. 49. — eBook ISBN 978-5-9775-0456-0.
- Соломенчук В.Г., Соломенчук П.Г. Железо ПК 2012 — Пб.: БХВ-Петербург, 2012. — С. 159-185.
- Bruce Jacob, Spencer W. Ng, and David T. Wang, with contributions by Samuel Rodriguez. Memory Systems: Cache, DRAM, Disk. — Morgan Kaufmann Publishers, September 2007. — С. 476-477. — ISBN 978-0123797513.